Harmonics suppression circuit for a switch-mode power amplifier
US9641141B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Feb 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Even harmonics are suppressed by a harmonics-reducing bias generator that drives bias voltages to cascode control transistors in series with driver transistors in a power amplifier. A first bias voltage is generated by mirroring pull-up currents in the power amplifier. A p-channel source transistor and a p-channel cascode current-mirror transistor also mirror the power amplifier pull-up current to a midpoint node. An n-channel sink transistor and an n-channel cascode current-mirror transistor mirror the pull-down current in the power amplifier to the midpoint node. An op amp compares the midpoint node to VDD/2, and drives the gate of a p-channel feedback transistor. Current from the p-channel feedback transistor flows through an n-channel cascode current-mirror transistor that generates a second bias voltage. The second bias voltage is adjusted until the midpoint node reaches VDD/2, causing the pull-up and pull-down currents in the power amplifier to better match, reducing even harmonics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.