Calibration techniques for SAR ADCs with on-chip reservoir capacitors
US9641189B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Jun 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
When reservoir capacitors are moved on-chip for individual bit decisions, a successive approximation register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.