Circuit arrangement and method for processing a digital video stream and for detecting a fault in a digital video stream, digital video system and computer readable program product
US9641809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2014 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Dec 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/89
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a circuit arrangement for processing a digital video stream, the circuit arrangement comprising: an input interface for receiving a digital video stream, a processing circuit which is arranged to process the digital video stream, a hang-up detecting circuit for detecting a fault in the processed digital video stream, the hang-up detecting circuit comprising: a checksum generating circuit which is arranged to generate checksums for the frames of the processed digital video stream, a memory for storing generated checksums and an analyzing device arranged to compare a currently generated checksum to a plurality of corresponding checksums of preceding frames stored in the memory and to generate an error signal if at least one predefined amount of compared checksums are matching. The present invention also relates to a digital video system, a method for processing a digital video stream and a computer readable program product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.