Emulation of fused multiply-add operations
US9645792B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2014 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | May 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/57
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.