Instruction and logic for processing text strings
US9645821B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2014 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Jan 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a decoder logic to decode a compare instruction, and an execution unit to execute the compare instruction. The compare instruction is to cause the processor to compare integer data elements of a first 64-bit SIMD integer operand with integer data elements of a second 64-bit SIMD integer operand. The integer data elements of the first 64-bit SIMD integer operand to be compared with the integer data elements of the second 64-bit SIMD integer operand are to be in same data element positions. The compare instruction is also to cause the processor to store a plurality of indicators of whether the compared integer data elements of the first and second 64-bit SIMD integer operands are equal. The plurality of indicators are expanded data elements, each of a first multi-bit size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.