Branch target address cache using hashed fetch addresses
US9645824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2012 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Apr 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit incorporates prefetch circuitry for prefetching program instructions from a memory. The prefetch circuitry includes a branch target address cache. The branch target address cache stores data indicative of branch target addresses of previously encountered branch instructions fetched from the memory. For each previously encountered branch instructions, the branch target address cache stores a tag value indicative of a fetch address of that previously encountered branch instruction. The tag values stored are generated by tag value generating circuitry which performs a hashing function upon a portion of the fetch address such that the tag value has a bit length less than the bit length of the portion of the fetch address concerned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.