Data storage device and flash memory control method
US9645895B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2014 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Jun 26, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to establish a first physical-to-logical address mapping table (F2H table) in a random access memory (RAM) for a first run-time write block containing MLCs. The microcontroller is further configured to establish a second F2H table in the RAM for a second run-time write block containing SLCs. When data that was previously stored in the first run-time write block with un-uploaded mapping information in the first F2H table is updated into the second run-time write block, the microcontroller is configured to update a logical-to-physical address mapping table (H2F table) in accordance with the first F2H table. The H2F table is provided within the flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.