System-on-chip and address translation method thereof using a translation lookaside buffer and a prefetch buffer
US9645934B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2014 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Oct 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page descriptor can be stored in advance in a memory management unit under various conditions so that an address translation overhead can be reduced. The memory management unit comprises an address translation unit that receives a memory access request as a virtual address and translates the virtual address to a physical address. A translation lookaside buffer (TLB) stores page descriptors of a plurality of physical addresses, the address translation unit determining whether a page descriptor corresponding to a received virtual address is present in the translation lookaside buffer. A prefetch buffer stores page descriptors of the plurality of physical addresses. The address translation unit, in the event the page descriptor corresponding to the received virtual address is not present in the translation lookaside buffer, further determines whether the page descriptor corresponding to the received virtual address is present in the prefetch buffer; updates the translation lookaside buffer with the page descriptor corresponding to the received virtual address; and performs a translation of the virtual address to a physical address using the page descriptor corresponding to the recei…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.