System and method for informing hardware to limit writing in a memory hierarchy
US9645936B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2015 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Jun 2, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and other embodiments associated with providing limited writing in a memory hierarchy are described. According to one embodiment, an apparatus includes a plurality of memory devices sequentially configured in a memory hierarchy. The apparatus also includes a first logic configured to execute a first command to initiate a sequence of write operations to write data to the plurality of memory devices in the memory hierarchy via propagation of the data sequentially through the memory hierarchy. The apparatus further includes a second logic configured to execute a second command to initiate an interruption of the sequence of write operations by indicating to at least one memory device of the plurality of memory devices to terminate the propagation of the data through the memory hierarchy prior to completing the propagation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.