Disruption counters
US9645955B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2014 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Sep 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is provided that includes a memory and one or more processors in communication with the memory. The one or more processors are configured to identify a set of targets and select a first value corresponding to a number of targets from the set of targets that can be concurrently disrupted. A second value is determined that is related to a number of disruptions actually occurring. A disruption request is received for a target of the set of targets. Thereafter, the first value is compared to the second value. Based on the comparison of the first and second values, it is determined whether to resist a requested disruption. If it is determined that the disruption is to be resisted, the requested disruption is resisted. If it is determined that the disruption is not to be resisted, at least one of the first value and the second value are adjusted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.