System and method for validating stacked dies by comparing connections
US9646128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2015 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | May 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.