Memory device with internal combination logic
US9646661B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 2016 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Feb 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.