Multi-bank memory with line tracking loop
US9646663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2015 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Jun 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.