Systems and methods for managing write voltages in a cross-point memory array
US9646671B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2016 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Oct 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for managing voltages applied to memory cells in a cross-point array during a write operation (e.g., to transition from a resistive state into a conductive state). The techniques apply to thyristor memory cells and non-thyristor memory cells. Bitlines, connected by a wordline, are preconditioned to a voltage level, by a precondition device, to write data to one or more memory cells at intersections of the bitlines and the wordline. Each bitline is coupled to a high impedance device, a detect device, a precondition device and a clamp device. When a memory cell on a first bitline transitions from a resistive state into a conductive state, it pulls a voltage level of the first-bit line level low. A first clamp device maintains the voltage level at a level to de-bias the first bitline from the wordline, while other memory cells to be written along the wordline remain biased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.