Non-volatile memory system with reset verification mechanism and method of operation thereof
US9646690B2 · kind B2 · utility
2Cited by
7References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2015 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Jun 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.