Wafer structure for electronic integrated circuit manufacturing
US9646835B2 · kind B2 · utility
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18References
6Claims
0Family size
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Key dates
| Filing date | Mar 3, 2016 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Mar 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.