System-on-chip devices and methods of designing a layout therefor
US9646960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2016 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Feb 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a first metal layer electrically connected to the active pattern and the gate electrode. The first metal layer may include a first metal line extending in the first direction and a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction. The first and second metal lines may include first and second sidewalls parallel to the second direction, the first and second sidewalls may face each other, and the first sidewall may have a length that is two or three times a minimum line width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.