Thin film transistor substrate and manufacturing method thereof
US9646996B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2014 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Mar 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/123
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array panel includes a first substrate, a gate line disposed on the first substrate and includes a lower layer including titanium, a middle layer including a transparent conductive material, and an upper layer including copper, a pixel electrode disposed on the first substrate and includes a lower layer including titanium, and an upper layer including the transparent conductive material, a gate insulating layer disposed on the gate line and the pixel electrode, a semiconductor layer disposed on the gate insulating layer, a data line and a drain electrode disposed on the semiconductor layer, a passivation layer which covers the data line and the drain electrode, and a common electrode disposed on the passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.