Array substrate, method for fabricating the same and display device
US9647001B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 13, 2013 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Feb 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes a base substrate, and further includes a metal shield layer, a semiconductor layer, a gate insulation layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer and a pixel electrode layer sequentially formed on the base substrate. At least one first via hole penetrating to the metal shield layer is formed in the interlayer dielectric layer and the gate insulation layer. The source-drain metal layer is formed in the at least one first via hole and on the interlayer dielectric layer having the at least one first via hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.