Electronic device including laterally arranged P-type and N-type regions in a two dimensional (2D) material layer and method of manufacturing the same
US9647166B2 · kind B2 · utility
1Cited by
2References
17Claims
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Key dates
| Filing date | Nov 26, 2014 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Nov 26, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/52
Abstract
According to example embodiments, an electronic device includes a substrate, an insulating layer on the substrate, and a diode layer on the insulating layer. The diode layer includes a two dimensional (2D) material layer. The 2D material layer includes an N-type region and a P-type region. According to example embodiments, a method of manufacturing an electronic device includes forming an insulating film on a substrate, forming a 2D material layer on the insulating film, and dividing the 2D material layer into an N-type region and a P-type region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.