Hybrid architecture for signal processing and signal processing accelerator
US9647667B1 · kind B1 · utility
6Cited by
7References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 14, 2015 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Apr 14, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for configuring circuitry for use with a field programmable gate array (FPGA) are disclosed. The circuitry includes an array of signal processing accelerators (SPAs) and an array of network nodes. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input signals from the FPGA. The array of network nodes controllably route the input signals to the array of SPAs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.