Apparatus for generating clock signals having a PLL part and synthesizer part with programmable output dividers
US9647674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2016 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Apr 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B19/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal generator responsive to synchronization pulses to perform actions has a phase locked loop (PLL) part including a digitally controlled oscillator (DCO) and an output driver coupled to the DCO, and a synthesizer part including a frequency synthesizer responsive to frequency and phase information from the DCO to generate a synthesized clock and programmable output dividers for generating output clocks from the synthesized clock. An interface establishes communication between the PLL part and the synthesizer part. The output driver is programmed to compute a phase offset required to align a selected output divider with the phase of the DCO and transmit the computed offset to the selected output divider over said interface for application to said selected output divider upon the occurrence of a synchronization pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.