Video decoding implementations for a graphics processing unit
US9648325B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2007 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Oct 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/89
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Video decoding innovations for multithreading implementations and graphics processor unit (“GPU”) implementations are described. For example, for multithreaded decoding, a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multithreading. Or, for a GPU implementation, a decoder uses innovations in the areas of inverse transforms, inverse quantization, fractional interpolation, intra prediction using waves, loop filtering using waves, memory usage and/or performance-adaptive loop filtering. Innovations are also described in the areas of error handling and recovery, determination of neighbor availability for operations such as context modeling and intra prediction, CABAC decoding, computation of collocated information for direct mode macroblocks in B slices, reduction of memory consumption, implementation of trick play modes, and picture dropping for quality adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.