Low quiescent current linear regulator circuit
US9651965B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2015 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Oct 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A linear regulator circuit includes a power transistor coupled between an input voltage node and an output voltage node. A control circuit of the linear regulator includes a feedback network having an input coupled to the output voltage node and an output configured to generate a feedback voltage. An error amplifier receives a reference voltage and the feedback voltage to generate an error signal. A driver circuit receives the error signal and has an output coupled to drive a control terminal of the power transistor. A first power supply terminal of the driver circuit is coupled to a first power supply node and a second power supply terminal of the driver circuit is coupled to the output voltage node. The bias current for operation of the driver circuit is accordingly directly sourced to the output voltage node to support low quiescent current operation of the regulator circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.