Apparatus for predicate calculation in processor instruction set
US9652242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2012 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Apr 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3854
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for calculating flag bits is disclosed. The flag bits may be used in a processor utilizing branch predication. More particularly, the apparatus and method may be used to calculate a predicate that can be used by a branch unit to evaluate whether a branch is to be taken. In one embodiment, the apparatus is coupled to receive a condition code associated with an instruction, and flag bits generated responsive to execution of the instruction. The condition code is indicative of a condition to be checked resulting from execution of the instruction. The apparatus may then provide an indication of whether the condition is true.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.