Multi-core RAM error detection and correction (EDAC) test
US9652315B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2015 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Oct 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for detection and correction of single-bit errors in a multi-core processing resource (MCPR) of an avionics processing system includes a RAM EDAC testing module called by the MCPR health monitor to access EDAC registers of a system-on-chip module coupled to the MCPR and access memory addresses passed by the MCPR health monitor to detect single-bit errors. Single-bit errors detected in memory mapped to the hypervisor are corrected by the RAM EDAC testing module. Single-bit errors detected in memory associated with a partition or core of the MCPR are corrected by the health monitor running on the particular partition or core with which the memory portion is associated. Single-bit errors may be detected in unmapped memory associated with a partition or core by accessing the unmapped memory via a temporary TLB entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.