Non-blocking memory management unit
US9652560B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2011 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Apr 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to handling page faults created by a processor unit. In some embodiments, such techniques may be used within the context of graphics processor units (GPUs) to reduce the chances that a page fault will result in a GPU-pipeline stall. In one embodiment, a processor includes a graphics processor pipeline and a memory management unit. The graphics processor pipeline includes a plurality of pipeline stages. The memory management unit is configured to determine that a first data request from a first of the plurality of pipeline stages causes a page fault, and to service requests from one or more others of the plurality of pipeline stages while the page fault is being serviced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.