Volatile semicondcutor memory device, refresh control circuit and method thereof
US9653142B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Apr 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A refresh control circuit of a volatile semiconductor memory device is provided, where the volatile semiconductor memory device includes a plurality of memory cells respectively having a select transistor and a memory element, and the refresh control circuit of the volatile semiconductor memory device includes: a first comparison part, which compares a memory voltage of the memory cell of the volatile semiconductor memory device that is different to a general-memorizing memory cell with a specified threshold voltage, and outputs a comparison result signal, and stops self refresh of the memory cell until the memory voltage is decreased to be smaller than the specified threshold voltage. The memory cell is formed in a region adjacent to an array of the general-memorizing memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.