Asymmetrical emphasis in a memory data bus driver
US9653147B1 · kind B1 · utility
13Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2015 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Dec 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The circuit may be configured to modify a read signal that transfers the read data across a read line to a memory controller. A filter may delay the memory signal to generate a delayed signal. A driver generally amplifies the memory signal to generate the read signal. The driver may modify the read signal with a de-emphasis on each pull up of the memory signal and a pre-emphasis on each pull down of the memory signal based on the delayed signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.