Methods for fabricating integrated circuits with low, medium, and/or high voltage transistors on an extremely thin silicon-on-insulator substrate
US9653365B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Apr 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
Abstract
A method for fabricating an integrated circuit that include providing or obtaining an extremely thin silicon-on-insulator (ETSOI) substrate, dividing the ETSOI substrate into a low voltage field effect transistor (FET) region and one or both of a medium voltage FET region and a high voltage FET regions, and forming a low voltage FET within the low voltage FET regions and forming a medium and/or high voltage FET within the medium and/or high voltage FET region(s). Channel, source, and drain structures of the low voltage FET are formed in an upper silicon layer that is disposed above a buried oxide layer of the ETSOI substrate, whereas channel, source, and drain structures of the medium and/or high voltage FETs are formed at least partially below the upper silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.