Logic cell, semiconductor device including logic cell, and method of manufacturing the logic cell and semiconductor device
US9653394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2015 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Feb 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/974
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.