Transistor with shield structure, packaged device, and method of manufacture
US9653410B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Mar 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor includes a semiconductor substrate having an intrinsic active device, a first terminal, and a second terminal. The transistor also includes an interconnect structure formed of multiple layers of dielectric material and electrically conductive material on an upper surface of the semiconductor substrate. The interconnect structure includes a pillar, a tap interconnect, and a shield structure formed from the electrically conductive material. The pillar electrically contacts the first terminal, extends through the dielectric material, and connects to a first runner. The tap interconnect electrically contacts the second terminal, extends through the dielectric material, and connects to a second runner. The shield structure extends from a shield runner through the dielectric material toward the semiconductor substrate. The shield structure is positioned between the pillar and the tap interconnect to limit feedback capacitance between the tap interconnect and the pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.