Power grid conductor placement within an integrated circuit
US9653413B2 · kind B2 · utility
10Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Jun 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit 2 is formed with standard-cell power conductors 14 which are overlaid by power grid conductors 20. The power grid conductors are offset in a direction transverse to the longitudinal axis of the power grid conductors relative to their underlying standard-cell power conductor. This has the effect of increasing the conductor spacing possible to one side of the power grid conductor. Accordingly, a wider than minimum width power grid conductor may be provided which blocks only one of its adjacent track positions from being used by a routing conductor 22.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.