Local interconnect layer enhanced ESD in a bipolar-CMOS-DMOS
US9653447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Sep 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.