Method for designing cascaded multi-level inverter with minimized large-scale voltage distortion
US9654025B2 · kind B2 · utility
0Cited by
0References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Dec 10, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for designing cascaded multi-level inverters with minimization of large-scale voltage distortion, based on KKT (Karush-Kuhn-Tucker) conditions and with simplified computation of conduction angles, simplifies the computation process, and is conducive to on-line calculation. Meanwhile, its fundamental voltage is adaptive, minimization of total harmonic is realized for cascaded multi-level inverters at high-voltage, and voltage power quality at grid connected nodes is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.