Phase locked loop and operating method thereof
US9654119B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Jun 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.