Systems and methods for providing a pipelined analog-to-digital converter
US9654126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2015 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Sep 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/442
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.