Capacitor order determination in an analog-to-digital converter
US9654131B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Feb 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.