Bi-directional parity bit generator circuit
US9654146B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2015 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Sep 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A parity bit generator module is disclosed that operates in a first direction or a second direction. In the first direction, the parity bit generator module generates parity bits for a first input datastream having information bits and combines these parity bits with the information bits of the input datastream to provide a first output datastream. Otherwise in a second direction, the parity bit generator module separates information bits from a second input datastream and generates parity bits from the information bits of the second input datastream to provide a second output datastream having the parity bits. In various exemplary embodiments, the bi-directional parity bit generator is implemented as part of an encoding/decoding module and/or an error-correcting code (ECC) data storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.