Reconfigurable ECC for memory
US9654148B2 · kind B2 · utility
5Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2015 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | May 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one general aspect, an apparatus may include a memory and a reconfigurable error correction array. The memory may be configured to store data. The reconfigurable error correction array may be configured to provide a plurality of levels of error correction to the memory based, at least in part, upon a number of errors detected within the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.