Power-aware CPU power grid design
US9658671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Jun 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for providing a power grid are provided. The apparatus includes a plurality of memory units comprising at least one SoC memory and at least one cache memory. The apparatus includes a first subsystem coupled to the at least one SoC memory associated with a first power domain. The apparatus further includes a second subsystem coupled to the at least one cache memory associated with a second power domain. The second subsystem may be a CPU subsystem. Because the first power domain sources power from a shared power source, the first power domain may operate at a voltage level that is higher than the operation of memory circuits requires. By moving the at least one cache memory from the first power domain to the second power domain, LDO efficiency loss for components in the first power domain may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.