Achieving power saving by a circuit including pluralities of processing cores based on status of the buffers used by the processing cores
US9658675B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Mar 20, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Subject matter disclosed herein relates to arrangements and techniques that provide for sending messages among processing nodes over a network-on-chip (NoC). More particularly, the present disclosure provides an Application Specific Integrated Circuit (ASIC) that includes processing cores and co-processors. The processing cores and co-processors are coupled together with a NoC. Each processing core and co-processor includes two corresponding buffers. A first buffer is for sending messages and a second buffer is for receiving messages. If a processing core or co-processor needs to send a message and the corresponding first buffer is full, if the message includes a flag that indicates a WAIT function, then the processing core and/or co-processor enters a low power state until the first buffer is available; otherwise the message is ignored and not sent. Additionally, if a second buffer is empty, then the corresponding processing core and/or co-processor enters the low power state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.