DRAM having SDRAM interface and flash memory consolidated memory module
US9658783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2013 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Mar 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In methods connecting a memory module configured from DRAM, which is high-speed memory, and a memory module configured from flash memory which is slower than DRAM but is high-capacity memory, to a CPU memory bus, in the case of sequential reading, the busy rate of the CPU memory bus increases, and performance degradation occurs easily. In the present invention, an information processing device has a CPU, a CPU memory bus, and a primary storage device. The primary storage device has a first memory module and a second memory module. The first memory module has high-speed memory. The second memory module has memory having the same memory interface as that of the high-speed memory, high-capacity memory having a different memory interface from that of the high-speed memory, and a controller that controls same. The first memory module and second memory module are caused to be accessed by the memory interface of the high-speed memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.