Instructions and logic to provide SIMD SM3 cryptographic hashing functionality
US9658854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Nov 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.