Patent · US Active

Malfunction escalation

US9658919B2 · kind B2 · utility

2Cited by

0References

14Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Chiloda Ashan Senerath Pathirane · Haverhill, GB
Allan John Skillman · Cambridge, GB

Key dates

Filing date	Apr 14, 2015
Grant date	May 23, 2017
Priority date	—
Expiry date	Jul 22, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1044
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A data processing apparatus includes error detection and correction circuitry with an associated hard-error memory buffer. When a correctable hard-error is detected associated with a memory access to a memory, if the hard-error memory buffer is already full, then this correctable hard-error is escalated to be handled as an uncorrectable hard-error. The escalated uncorrectable hard-error is then handled by uncorrectable error handling circuitry (fatal error circuitry) which may trigger an abort of corresponding processing operations by a processor core and force the relinquishing of resources within other circuit elements such as a store buffer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.