Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques
US9659138B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Nov 16, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal track pattern is generated by arranging multiple tracks in an order and further by associating the first width with the first track in the custom, legal track pattern. The layout may then be further modified by guiding the insertion of one or more additional shapes with the custom, legal track pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.