Semiconductor memory device and method for manufacturing same
US9659957B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 18, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Feb 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/00
Abstract
According to one embodiment, a semiconductor memory device includes a first stacked body including a plurality of first electrode layers and a plurality of first insulating layers, the first electrode layers separately stacked each other, the first insulating layers provided between the first electrode layers; a second stacked body including a plurality of second electrode layers and a plurality of second insulating layers, the second electrode layers separately stacked each other, the second insulating layers provided between the second electrode layers, the second stacked body separated from the first stacked body in a first direction crossing a stacking direction of the first stacked body; and a first insulating portion provided between the first stacked body and the second stacked body, the first insulating portion provided integrally to the first insulating layers and the second insulating layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.