Three-dimensional semiconductor memory device
US9659958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Oct 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.