Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same
US9660020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2014 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Aug 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes a p-type semiconductor substrate, an n-type epitaxial layer disposed over and in contact with the p-type semiconductor substrate, and a p-type implant layer disposed within the n-type epitaxial layer, wherein the p-type implant layer is not in contact with the p-type semiconductor substrate. It further includes an n-type reduced surface field region disposed over and in contact with the p-type implant layer, a p-type body well disposed on a lateral side of the p-type implant layer and the n-type reduced surface field region, and a shallow trench isolation (STI) structure disposed within the n-type reduced surface field region. Still further, it includes a gate structure disposed partially over the p-type body well, partially over the n-type surface field region, and partially over the STI structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.