Apparatus and method to perform a double correlation
US9660692B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2014 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Feb 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0611
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An apparatus is described for performing a correlation function on a received signal and a plurality of predetermined chip codes from a communication standard. The apparatus comprising: a first plurality of logic gates configured as a multiplier unit operable to receive a signal sampled at a predetermined sampling frequency, and to perform predetermined multiplication operations on the input signal in accordance with the correlation function; a first memory unit operable to receive and store multiplication values from the first plurality of logic gates; a second memory unit having stored therein values from predetermined multiplication operations performed on the plurality of chip codes in accordance with the correlation function; and a second plurality of logic gates configured as an adder unit to receive multiplication values outputted from the first memory unit and the second memory unit and to sum the multiplication values from the first memory unit taking into account the multiplication values in the from the second memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.